Foez Ahmed
Founder & Lead Engineer

Foez Ahmed

Senior RTL and verification engineer with extensive hands-on experience across high-speed ASIC design, cache controllers, complex bus fabric, and SoC integration. Foez works end-to-end — from initial micro-architecture definition through lint-clean, CDC-safe synthesis handoff — embedding directly into client teams with zero ramp-up overhead.

SystemVerilog UVM Formal Verification CDC Analysis Verilog VHDL Python Tcl SVA / PSL

Technical Depth

Spanning the complete ASIC front-end flow — from architecture through synthesis handoff — with deep specialization in UVM-based functional verification, formal techniques, and CDC-safe design.

RTL Design

  • Microarchitecture definition and refinement
  • SystemVerilog, Verilog & VHDL RTL development
  • FSM, datapath, and control logic design
  • High-speed bus fabric and cache controller design
  • Low-power aware RTL implementation
  • Parameterized and reusable IP development

Functional Verification

  • UVM testbench architecture from scratch
  • Constrained-random stimulus and coverage closure
  • SVA and PSL assertion development
  • Formal property checking and equivalence
  • Gate-level simulation and SDF annotation
  • 95%+ functional coverage as standard target

Design Quality and Signoff

  • RTL linting to zero violations
  • CDC and RDC analysis and closure
  • Coding guideline enforcement
  • Synthesis-ready handoff preparation
  • Signoff checklist definition and execution

Automation and Tooling

  • Python-based regression orchestration
  • Tcl EDA tool scripting
  • Automated coverage merging and reporting
  • HTML dashboards for KPI visibility
  • CI/CD integration for simulation flows

Methodology and Documentation

  • Verification plan authorship
  • RTL coding guideline definition
  • Micro-architecture documentation
  • Review checklist development
  • Knowledge-transfer package preparation

Consulting and Leadership

  • Architecture and strategy consulting
  • Technical review facilitation
  • Project risk identification and recovery
  • Cross-team coordination
  • Engineering process improvement

How We Engage

Every engagement is built on directness, transparency, and a relentless focus on first-time-right quality.

Embedded in Your Flow

  • Works within your EDA toolchain and licensing
  • Uses your SCM, review, and communication tools
  • Productive from day one — no ramp-up lag
  • Adapts to your process standards

Zero-Defect RTL Philosophy

  • Lint-clean deliverables as non-negotiable baseline
  • CDC/RDC analysis on every design
  • Review-ready documentation every time
  • No escapes through first-pass review

Transparent Communication

  • Daily status when on active engagements
  • Early warning on schedule risks
  • Clear milestone tracking and reporting
  • Full NDA coverage on all project communications

The Journey

Born in Bangladesh's dynamic metropolis of Sylhet, where modern innovation coexists with historic heritage. I have always been interested in the invisible forces that influence our world. For me, subjects like computer architecture, digital technology, and electronics were more than simply academic subjects — they were the things that stoked my imagination and piqued my interest.

I obtained a Bachelor of Science in Electrical and Electronic Engineering from Shahjalal University of Science and Technology. University evolved into a hive of ideas where theory became practice. I jumped right into difficult tasks, constantly curious to see what else might be accomplished and to come up with original answers to difficult problems.

I started a new chapter in my life in 2022 when I became an RTL Design & Verification Engineer at DSi. Being hired for the first time was an exciting and humbling experience. I thoroughly studied the subtleties of AMBA system connection protocols, which provided me with the assurance I needed to successfully negotiate challenging technical situations.

My motivation has always been to take on challenges. I assumed leadership of a group tasked with developing and confirming a System-on-Chip (SoC) based on RV64G. Being the team leader meant more than just meeting goals — it meant fostering a culture of cooperation where creativity could flourish. Together, we not only accomplished our goals but also raised the bar for productivity and innovation throughout the organisation.

I really think that teaching is the best way to learn outside of the workplace. Not only does sharing my knowledge help others, but it also strengthens my own comprehension. My personal values are centred on mentoring and education, and I get great satisfaction from seeing the development of people I assist.

My aspirations are both ambitious and intimate: to consistently advance both professionally and spiritually. Real success involves more than just moving up the professional ladder — it also involves personal growth and fulfilment. This all-encompassing strategy encourages me to pursue knowledge constantly, welcome novel experiences, and exercise empathy.

Helping others in need is something I truly appreciate at my core. This altruistic way of thinking has improved my life and made my relationships with the community stronger. My goal is to leave a legacy of kindness, wisdom, and inspiration, characterised by the positive influence I've had on others.

In my opinion, the relationships we make and the lives we impact along the road define our journeys more so than the things we accomplish. I welcome you to join me — together, we can set off on a path of creativity, development, and collective achievement.

Start Your Next Project

Currently accepting new engagements. Describe your silicon challenge and expect a concrete response within 24 hours.

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